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? semiconductor components industries, llc, 2015 february, 2015 ? rev. 2 1 publication order number: mc74hc4094a/d mc74hc4094a 8-bit shift and store register high?performance silicon?gate cmos the mc74hc4094a is a high speed cmos 8?bit serial shift and storage register. this device consists of an 8?bit shift register and latch with 3?state output buffers. data is shifted on positive clock (cp) transitions. the data in the shift register is transferred to the storage register when the strobe (str) input is high. the output buffers are enabled when the output enable (oe) input is set high. two serial outputs (qs 1 , qs 2 ) are available for cascading multiple devices. features ? wide operating voltage range: 2.0 to 6.0 v ? low power dissipation: i cc = < 10 a ? in compliance with the requirements defined by jedec standard no. 7a ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these are pb?free devices typical applications ? serial?to?parallel conversion ? remote control storage register www. onsemi.com marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g, = pb?free package see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information soic?16 d suffix case 751b tssop?16 dt suffix case 948f 1 16 1 16 1 16 hc4094ag awlyww hc 4094a alyw 1 16 (note: microdot may be in either location)
mc74hc4094a www. onsemi.com 2 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 qp 6 qp 5 qp 4 oe v cc qs 1 qs 2 qp 7 qp 0 cp d str gnd qp 3 qp 2 qp 1 figure 1. pin assignment figure 2. logic symbol figure 3. iec logic symbol cp str 31 2 9 10 4 5 6 7 14 13 12 11 15 d d oe qs1 qs2 qp0 qp1 qp2 qp3 qp4 qp5 qp6 qp7 3 1 2 9 10 4 5 6 7 14 13 12 11 15 1 d 2 d 3 c1/ srg8 c2 en3 figure 4. functional diagram 8 ? stage shift register 8 ? bit storage register 3 ? stage outputs qp0 qp1 qp2 qp3 qp4 qp5 qp6 qp7 4 5 6 7 14 13 12 11 2 3 1 15 10 9 d cp str oe qs2 qs1
mc74hc4094a www. onsemi.com 3 figure 5. logic diagram qp 1 qp 2 qp 3 qp 4 qp 5 qp 6 d cp str oe stages 1 to 6 stage 0 stage 7 qp 7 qp 0 qs 1 qs 2 d cp q ff0 d cp q latch d cp q ff7 d cp q latch d cp q latch cp d q
mc74hc4094a www. onsemi.com 4 maximum ratings symbol parameter value unit v cc dc supply voltage (referenced to gnd) ? 0.5 to + 7.0 v v in dc input voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 35 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air, soic package? tssop package? 500 450 mw t stg storage temperature ? 65 to + 150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ?derating ? soic package: ? 7 mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ?55 +125 c t r , t f input rise and fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 500 400 ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc4094a www. onsemi.com 5 functional table inputs parallel outputs serial outputs cp oe str d qp0 qpn qs1 qs2 l x x z z q?6 nc l x x z z nc qp7 h l x nc nc q?6 nc h h l l qpn?1 q?6 nc h h h h qpn?1 q?6 nc h h h nc nc nc qp7 notes 1. h = high voltage level l = low voltage level x = don?t care z = high impedance off?state nc = no change = low?to?high cp transition = high?to?low cp transition q?6 = the information in the seventh register stage is transferred to the 8th register stage and qsn output at the positive clo ck edge figure 6. timing diagram clock input data input strobe input output enable input internal q? 0 output internal q? 6 output serial output serial output cp d str oe ff0 qp 0 ff6 qp 6 qs 1 qs 2 z?state z?state
mc74hc4094a www. onsemi.com 6 dc characteristics symbo l parameter test conditions v cc (v ) guaranteed limits uni t ?55 c to 25 c 85 c 125 c v ih minimum high?level input voltage v out = 0.1 v or v cc ? 0.1 v ? i out ? 20 a 2.0 1.5 1.5 1.5 v 3.0 2.1 2.1 2.1 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 v il maximum low?level input voltage v out = 0.1 v or v cc ? 0.1 v ? i out ? 20 a 2.0 0.5 0.5 0.5 v 3.0 0.9 0.9 0.9 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 v oh minimum high?level output voltage v in = v ih or v il ? i out ? 20 a 2.0 1.9 1.9 1.9 v 3.0 2.9 2.9 2.9 4.5 4.4 4.4 4.4 6.0 5.9 5.9 5.9 v in = v ih or v il , ? i out ? = 2.4 ma 3.0 2.75 2.7 2.6 v in = v ih or v il , ? i out ? = 4 ma 4.5 4.25 4.2 4.1 v in = v ih or v il , ? i out ? = 5.2 ma 6.0 5.75 5.7 5.6 v ol maximum low?level output voltage v in = v ih or v il , ? i out ? 20 a 2.0 0.1 0.1 0.1 v 3.0 0.1 0.1 0.1 4.5 0.1 0.1 0.1 6.0 0.1 0.1 0.1 v in = v ih or v il , ? i out ? = 2.4 ma 3.0 0.25 0.3 0.4 v in = v ih or v il , ? i out ? = 4 ma 4.5 0.25 0.3 0.4 v in = v ih or v il , ? i out ? = 5.2 ma 6.0 0.25 0.3 0.4 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1 1 a i oz maximum tri?state output leakage current v in = v cc or gnd v out = v cc or gnd 6.0 0.5 5 10 a i cc maximum quiescent supply current v in = v cc or gnd 6.0 4.0 40 80 a
mc74hc4094a www. onsemi.com 7 ac characteristics (t f = t r = 6 ns, c l = 50 pf) symbol parameter test conditions v cc (v ) guaranteed limits uni t ?55 c to 25 c 85 c 125 c t phl , t plh maximum propagation delay cp to qs 1 figure 7 2.0 120 150 170 ns 3.0 90 100 110 4.5 30 38 45 6.0 26 33 38 t phl , t plh maximum propagation delay cp to qs 2 figure 7 2.0 120 150 170 ns 3.0 90 100 110 4.5 27 34 41 6.0 23 29 35 t phl , t plh maximum propagation delay cp to qp n figure 7 2.0 120 150 170 ns 3.0 90 100 110 4.5 39 49 59 6.0 33 42 50 t phl , t plh maximum propagation delay str to qp n figure 8 2.0 120 150 170 ns 3.0 90 100 110 4.5 36 45 54 6.0 31 38 46 t pzh , t pzl maximum 3?state output enable time oe to qp n figure 9 2.0 120 140 160 ns 3.0 80 100 120 4.5 35 44 53 6.0 30 37 45 t phz , t plz maximum 3?state output enable time oe to qp n figure 9 2.0 100 120 140 ns 3.0 70 90 110 4.5 25 31 38 6.0 21 26 32 t thl , t tlh maximum output transition time figure 7 2.0 70 90 110 ns 3.0 40 60 80 4.5 18 22 25 6.0 16 19 22 t w minimum clock pulse width high or low figure 7 2.0 80 100 120 ns 3.0 50 60 80 4.5 16 20 24 6.0 14 17 20 t w minimum strobe pulse width high figure 8 2.0 80 100 120 ns 3.0 50 60 80 4.5 16 20 24 6.0 14 17 20 t su minimum set?up time d to cp figure 10 2.0 50 65 75 ns 3.0 30 35 45 4.5 10 13 15 6.0 9 11 13
mc74hc4094a www. onsemi.com 8 ac characteristics (t f = t r = 6 ns, c l = 50 pf) symbol unit guaranteed limits v cc (v) test conditions parameter symbol unit 125 c 85 c ?55 c to 25 c v cc (v) test conditions parameter t su minimum set?up time cp to str figure 8 2.0 100 125 150 ns 3.0 60 75 90 4.5 20 25 30 6.0 17 21 26 t h minimum hold time d to cp figure 10 2.0 3 3 3 ns 3.0 3 3 3 4.5 3 3 3 6.0 3 3 3 t h minimum hold time cp to str figure 8 2.0 0 0 0 ns 3.0 0 0 0 4.5 0 0 0 6.0 0 0 0 f max minimum clock pulse frequency figure 7 2.0 6 5 4 mhz 3.0 18 14 12 4.5 30 24 20 6.0 35 28 24 c in maximum input capacitance ? 10 10 10 pf c out maximum output capacitance ? 15 15 15 pf c pd power dissipation capacitance (note 2) ? 140 140 140 pf 2. c pd is defined as the value of the ic?s equivalent capacitance from which the operating current can be calculated from: i cc (operating) c pd x v cc x f in x n sw where n sw = total number of outputs switching and f in = switching frequency.
mc74hc4094a www. onsemi.com 9 ac waveforms figure 7. waveforms showing the clock (cp) to output (qpn, qs1, qs2) propagation delays, the clock pulse width and the maximum clock frequency. figure 8. waveforms showing the strobe (str) to output (qpn) propagation delays, the strobe pulse width, the clock set?up and hold times for the strobe input. figure 9. waveforms showing the 3?state enable and disable times for input oe. figure 10. waveforms showing the data set?up and hold times for the data input. the shaded areas indicate when the input is permitted to change for predictable output performance. t plh t phl t w 1/f max t tlh t thl cp input qp n , qs 1 output qs 2 output 50% t plh 50% t phl t thl t tlh t phl cp input qp n output t su t h t plh t w str input t f t r 90% t pzl 10% outputs enabled outputs enabled t pzh t plz t phz oe input qp n output: low ? to ? off off ? to ? low qp n output: high ? to ? off off ? to ? high outputs disabled 10% 90%
mc74hc4094a www. onsemi.com 10 test circuits *includes all probe and jig capacitance c l * test point device under test output *includes all probe and jig capacitance c l * test point device under test output connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . 1 k figure 11. ac characteristics load circuits ordering information device package shipping ? mc74hc4094adg soic?16 (pb?free) 48 units / rail mc74hc4094adr2g soic?16 (pb?free) 2500 / tape & reel MC74HC4094ADTG tssop?16 (pb?free) 96 units / rail mc74hc4094adtr2g tssop?16 (pb?free) 2500 / tape & reel nlvhc4094bdtr2g* tssop?16 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
mc74hc4094a www. onsemi.com 11 package dimensions tssop?16 dt suffix case 948f issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hc4094a www. onsemi.com 12 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74hc4094a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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